In microelectronics and microsystems technology, apart from reducing the lateral dimensions, i.e. the dimensions in the area of a suitable substrate, e.g. a semiconductor wafer, there is an increasing tendency to also create an interconnection in the dimension perpendicular to the substrates in order to enable an overall three-dimensional integration. Especially the integration of micromechanical systems in combination with CMOS technology plays a central role in this development. Electrical vertical vias are important components for electrically interconnecting component structures, e.g. microelectromechanical structures (MEMS), electronic structures, e.g. CMOS structures including transistors, and the like, to other component structures arranged on the same substrate in different positions, or on an opposite substrate side or on a separate substrate. In such three-dimensional applications, the focus is often on the connection and stacking, respectively, of similar component structures, for example, stacking of memory or logic chips. The so-called heterogeneous integration is also used when striving for a more compact design of larger electronic units, wherein different construction types are connected, e.g. when chips without a housing are directly connected to printed circuit boards.
The vertical electrical via (also referred to as “through-connection ”) employed for these applications, especially for the through-connection of a semiconductor wafer, is suitable for versatile applications in microelectronics/microsystems technology and is thus provided as a suitable means in many new developments.
In general, an electrical vertical via is to be understood as a narrow hole extending through the semiconductor substrate, the wall of which is provided which an insulation layer and is filled with a conductive material. In recent developments, especially a metal or metal alloy has been used, at least in part, as the conductive material. The conductive material or metal is connected to the nearest contact level and thus achieves the desired conductivity for the via. Usually, it is intended that the dimensions of a via are as small as possible in order to save valuable space on the substrate and to keep the material costs low. When using an electrical via, the design and the production method are often adapted to the specific use of the via. The design of the via and the process control for producing the via are thus often dependent on component structure to be produced or produced which is provided on the substrate front side and/or substrate backside. In this adaptation between the production and type of the via as well as the type and production of the component structures, the time in the process chain, at which the via is produced, is important.
In general, there are three possible times for the production of a via, wherein a mix of these three times is possible in some cases, i.e. only a partial production at certain production times:                Via-First        The vertical via is produced first and then the component structures, e.g. MEMS/CMOS structures, are produced on the front side and/or backside of the substrate.        Via-Middle        The production processes for the via are performed during the production of the component structure, but are carried out prior to producing the metallization layers serving the purpose of connecting the individual components of the component structure (BEOL).        Via-Last        The via is produced only during or after the production of the metallization layers for the component structures.        
The policy to be applied is usually selected depending on the component structure to be produced in order to utilize the advantages of the respective policy while minimizing the disadvantages associated therewith in the light of the entire production method. Especially the mechanical and thermal influences of the production processes for the via are of great significance with respect to compatibility with the component structures to be produced or produced, e.g. with the CMOS/MEMS modules.
Thus, the approach “via-first” or “via-middle” is selected for standard applications of vias in order to keep corresponding compatibility problems between the process control for the via and the component structure low.
Due to the numerous different specifications for the applications of vertical vias, usually a corresponding new variant of the via is to be developed for each newly developed technology of the component structures. Already existing process policies for producing the vias are often already specialized too much to enable a modular flexible application. For example, the application field is severely limited by the approach “via-first” or “via-middle”, since the contamination of standard semiconductor processes is highly problematic when using metals, such as copper, as an example. In particular, many process plants are equipped with devices for handling the semiconductor wafers on their backsides by means of vacuum, which is why the previously processed wafer backside can be used in such plants in a limited way only. Significant problems also arise with respect to the conductive material of the via. Copper, which is used most often for this purpose, leads to an excessive difference in the temperature coefficient as compared to the semiconductor substrate, and it also diffuses into the adjacent material structures until a copper saturation is achieved therein, unless corresponding protective intermediate layers are provided. These properties of copper and also the plastic-elastic properties thereof can lead to considerable problems regarding material separation and adhesion, and/or also contribute to mechanical stress in the various material layers.
Furthermore, the effect of the surrounding atmosphere on copper layers is typically associated with a temperature-dependent oxidation of this layer which is to the disadvantage of conductivity.
The deposition of layers in vertical vias for greater aspect ratios can also be realized with great difficulty only, especially when a relatively complex layer structure, as in copper, is required.
Especially in the case of great aspect ratios, common methods for layer deposition reach their limits in terms of the deposition rates to be achieved and the expenditure of time required as a result, which limits are incompatible with the usual standards for mass production.
Substantial costs are incurred with respect to the material when especially copper or tungsten are used as conductive materials for a via.